LTED: A Canonical and Compact Hybrid Word- Boolean Representation as a Formal Model for Hardware/Software Co-designs
نویسندگان
چکیده
In this paper, we describe a hybrid bitand word-level representation called Linear Taylor Expansion Diagram (LTED) [1]. This representation not only has a compact and canonical form, but also is close to hardware-software descriptions so that it can be utilized as a formal model for formal verification and synthesis. The power of abstraction of LTED allows us to represent system level of hardware/software co-designs as well as implementation designs efficiently with run time requirements several orders of magnitude smaller than those of other known bit and word level representations discussed in the literature of formal verification. In order to evaluate the performance of LTED as a hybrid representation, it is run on some industrial designs and experimental results are compared with Taylor Expansion Diagram (TED) which is also a word level canonical representation [2].
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